MICROELECTRONICS - ULSI
The Room Temperature Wet Chemical Growth (RTWCG) of Insulating Films for Ultra Large Scale Integration (ULSI).
Integrated circuit miniaturization continues to well below the half-micron level in the quest for higher speed and greater efficiency. At such reduced dimensions, the relatively high dielectric constant and resulting capacitance of conventional interlayer dielectric materials works to limit signal speed, create cross-talk and consume excessive power.
The search continues for alternatives to SiO2 layers for many microelectronic device applications. For lower than 0.25m gap fill requirements, the search is now on for low dielectric constants that can work well with metal deposition and planarization schemes. For 0.35m gaps, fluorinated oxides, such as the silicon oxyfluorides (SiOF), which can have a dielectric constant as low as 3.2 (compared to about 3.9 for typical SiO2 films), provide the easiest way to accomplish this. The HDP-CVD deposited SiOF has already been used to fill 0.35m, and 0.25m gaps, and is also a contender even for the 0.18m gaps. However, the HDP-CVD has proven very difficult to implement even for the 0.25m gaps. Stability is the greatest concern for the HDP-CVD deposited SiOF films.
For future ULSI, Semiconductor Roadmap calls for dielectrics with k=2.5-3.0 for 0.18 mm devices and 2.0-2.5 at 0.15 mm or 0.13 mm. For various reasons oxide layers will continue to be used with low-k dielectrics. For gaps of 0.25m, 0.18m, 0.13m, 0.10m and lower, a variety of materials that can provide dielectric constants between 2 and 3 are under development (e.g. fluorinated
polyimide, non-polyimide C-H polymers, fluoro-polymers, siloxane polymers and parylenes, to name a few). All of these materials are just now beginning to be fully characterized. Thus far, the biggest common concerns are their relatively poor step coverage, low thermal conductivity, and lack of stability.
Some of the concerns associated with the above growth or deposition technologies of low dielectric constant insulators for Si-based ULSI applications are:
- poor compatibility with multilevel interconnection;
- deposition and post deposition treatments (e.g. planarization) introduce stress and chemical and particle contamination;
- relatively poor thermal, UV, and plasma stability;
- high temperature;
- low deposition rate;
- relatively poor step coverage;
- high investment cost.
Hence, a selective RTWCG of SiOX films for fully planarized multilevel interconnections, is attractive for VLSI and ULSI device applications, by eliminating the CMP process.
SPECMAT, Inc. has demonstrated the use of its revolutionary RTWCG process to grow low dielectric constant (2<k<3) stable SiO-based dielectric films capable of filling high aspect ratio nano-sized features. We have also demonstrates that the SPECMAT proprietary RTWCG process has competitive merits compared to other dielectric growth/deposition techniques for a variety of deep submicron IC's applications.